In the following, explanation will be provided for a switching power supply device in the prior art with reference to annexed figures.
FIG. 9 is a diagram illustrating an example of the constitution of switching power supply device 1a of the prior art. As shown in this figure, switching power supply device 1a is a power supply device for obtaining a prescribed stable DC voltage from a DC voltage that varies over a wide range and is obtained from a nickel-mercury battery or other battery (Bat in the figure) set on the input side.
As shown in the figure, switching power supply device 1a contains an H bridge type switching circuit composed of semiconductor switching elements Tr1, Tr2 set on the input side via inductance L, and semiconductor switching elements Tr3, Tr4 set on the output side. By controlling the ON state of said semiconductor switching elements, it is possible to realize step-up or step-down control. For example, the semiconductor switching elements can be controlled so as to obtain a stable 3 V output voltage from an input voltage that varies over a wide range of 1.5–5 V.
A PWM control signal to be explained later is fed from control part 10a via buffer Buf1 and inverter Inv2 to semiconductor switching elements Tr1 and Tr2 set on the input side. Consequently, semiconductor switching elements Tr1 and Tr2 are controlled so that one is ON while the other is OFF corresponding to the pulse width of the PWM control signal fed to the control part.
In the following, as shown in FIG. 9, the controller on the input side and composed of semiconductor switching elements Tr1, Tr2, buffer Buf1 and inverter Inv2 will be known as primary circuit (PR1).
The PWM control signal to be explained later is fed from control part 10a via buffer Buf3 and inverter Inv4 to semiconductor switching elements Tr3 and Tr4 set on the output side. Consequently, semiconductor switching elements Tr3 and Tr4 are controlled so that one is ON while the other is OFF corresponding to the pulse width of the PWM control signal fed to the control part.
In the following, as shown in FIG. 9, the controller on the input side composed of semiconductor switching elements Tr3, Tr4, buffer Buf3 and inverter Inv4 will be known as secondary circuit (SEC).
Input potential detecting part 20 always detects input potential Vin based on a prescribed reference potential, and it feeds the detected input potential Vin to control part 10a. As to be explained later, control part 10a switches the control mode corresponding to input potential Vin detected by input potential detecting part 20.
Transconductance amplifier 40 is a so-called Gm amplifier.
As shown in FIG. 9, the positive terminal of transconductance amplifier 40 has prescribed reference voltage Vref input to it, and a voltage obtained by voltage dividing output potential Vout by resistors RF and RS is input to its negative terminal.
Resistor R1 that generates a potential corresponding to the current output from transconductance amplifier 40 and capacitor C1 that performs phase compensation and is connected in series to said resistor R1 are connected to the output terminal of transconductance amplifier 40. Said capacitor C1 for phase compensation should have a relatively large capacitance, such as a capacitance of about 10 nF.
Also, the output terminal of transconductance amplifier 40 is connected to the negative terminal of comparator 50a. Consequently, the negative terminal of comparator 50a becomes the potential of the output terminal of transconductance amplifier 40 that has its phase compensated. On the other hand, a triangular signal with a prescribed period and a prescribed amplitude and generated in triangular wave generating part 30 is input to the positive terminal of comparator 50a. 
As a result, comparator 50a generates a clock signal with a duty ratio corresponding to the potential of the output terminal of transconductance amplifier 40. As shown in FIG. 9, the output terminal of comparator 50a is connected to output terminal c of control part 10a and, as to be explained later, said clock signal is inverted or not inverted corresponding to the control mode and is fed as an FB_PWM signal to either of the primary circuit/secondary circuit.
Control part 10a switches the control mode corresponding to input potential Vin detected by input potential detecting part 20. That is, when it is judged that input potential Vin is higher than target output potential Vout (Vin>Vout), control is performed to switch the control mode to the step-down control mode. On the other hand, when it is judged that input potential Vin is lower than target output potential Vout (Vin<Vout), control is performed to switch the control mode to the step-up control mode.
More specifically, in the step-down control mode, control part 10a takes the clock signal sent from comparator 50a as an FB_PWM signal, and feeds it to the primary circuit, and, simultaneously, it feeds an FF_PWM signal with a pulse width that can obtain a virtual output potential Vout (virtual Vout) to the secondary circuit.
Virtual Vout is the average potential on the side of the secondary circuit, and it satisfies the following relationship:VirtualVout=Vin×FBduty  (1)
On the other hand, in the step-up control mode, control part 10a takes the signal obtained by inverting the clock signal sent from comparator 50a as an FB_PWM signal and feeds it to the secondary circuit, and, simultaneously, it feeds an FF_PWM signal with a pulse width that can obtain a virtual input potential Vin (virtual Vin) to the primary circuit.
Virtual Vin is the average potential on the side of the primary circuit, and the following relationship is satisfied.VirtualVin=Vout×FBduty  (2)
Also, the processing for inverting the clock signal output from comparator 50a and generating the FB_PWM signal is performed by including a logic circuit containing an inverter in control part 10a. 
FIG. 10 is an equivalent circuit indicating the connection state and feeding state of a PWM signal when switching power supply device 1a operates in the step-down control mode.
In the step-up control mode with input potential Vin higher than output potential Vout, as shown in the figure, an FB_PWM signal with duty ratio (FBduty) corresponding to output potential Vout is fed to the primary circuit, and, simultaneously, an FF_PWM signal is fed to the secondary circuit. As a result, switching power supply device 1a performs step-down control to obtain target output potential Vout.
FIG. 11 is a diagram illustrating the state of connection and the PWM signal feeding state in case switching power supply device 1a performs the step-up control mode of operation.
In practice, the clock signal output from comparator 50a is inverted, and the obtained signal is fed as an FB_PWM signal to the secondary circuit. In order to simplify the description, different from comparator 50a shown in FIG. 10, for comparator 50a shown in FIG. 11, the positive terminal and negative terminal are reversed in the description, and it can be described that the output is equivalently fed to the secondary circuit directly.
When input potential Vin becomes lower then output potential Vout, the control mode becomes the step-up control mode, and, as shown in the figure, while the FB_PWM signal of duty ratio (FBduty) corresponding to the output voltage is fed to the secondary circuit, the FF_PWM signal is fed to the primary circuit. As a result, switching power supply device 1a performs step-up control so that target output potential Vout is obtained.
However, in said conventional switching power supply device 1a of the prior art, when the control mode is switched, a ripple voltage appear at the output of switching power supply device 1a due to the transient characteristics of the potential at the output terminal of transconductance amplifier 40 when the control mode is switched. That is, due to the presence of phase compensating capacitor C1 with a relatively large capacitance, it is impossible to realize stable control of output potential Vout in the transient region from immediately after switching of the control mode to stabilization of the potential at the output terminal of transconductance amplifier 40. This is undesired.
In the following, explanation will be provided in more detail on the aforementioned problem with respect to FIG. 12.
FIG. 12 illustrates the timing charts of various signal waveforms before and after switching time Tc of the control mode. (a) shows potential V40 at the output terminal of transconductance amplifier 40; (b) shows triangular signal Vtri input to comparator 50a; (c) shows the FB_PWM signal; (d) shows the FF_PWM signal; and (e) shows output potential Vout. The maximum potential of triangular signal Vtri is called Vtri2, and the minimum potential is called Vtri1.
As shown in FIG. 12, before time Tc, the relationship of input potential Vin>output potential Vout exists, and control part 10a operates in the step-down control mode. After time Tc, the relationship of input potential Vin<output potential Vout exists, and control part 10a operates in the step-up control mode. In this case, duty ratio FBduty of the FB_PWM signal is always set at the target value of 0.9.
Before time Tc, in order to stabilize potential V40 of the output terminal of transconductance amplifier 40, an FB_PWM signal with duty ratio FBduty shown in following formula (1) is fed to the primary circuit.FBduty=(V40−Vtri1)/(Vtri2−Vtri1)  (3)
For example, if Vtri2=1.45 V and Vtri1=0.85 V, when duty ratio FBduty of the FB_PWM signal is said 0.9, according to said formula (3), one has V40=1.39 V.
Then, at time Tc when input potential Vin falls to obtain the relationship of input potential Vin<output potential Vout, control part 10a starts the step-up control mode of operation. That is, immediately after time Tc, the clock signal output from comparator 50a is inverted and fed to the secondary circuit.
If a phase compensating capacitor C1 is not connected to the output terminal of transconductance amplifier 40, control is performed so that potential V40 of its output terminal quickly changes from 1.39 V (FBduty=0.9) before time Tc to 0.91 V.
Also, in the step-up control mode, because control part 10a inverts the clock signal output from comparator 50a to generate an FB_PWM signal, 0.91 V corresponds to FBduty=0.9 in the step-up control mode.
That is, according to said formula (2), an FF_PWM signal is fed to the primary circuit such that virtual Vin becomes 2.7 V (virtual Vin=output potential Vout×FBduty=3×0.9=2.7 V).
However, in practice, because a phase compensating capacitor C1 is not present, as shown in FIG. 12a, potential V40 of the output terminal immediately after time Tc gradually falls, and it takes certain time to reach the stable point of V40=0.91 V.
For example, if output potential V40 immediately after time Tc is the same as before time Tc, that is, 1.39 V, in the step-up control mode, because control part 10a inverts the clock signal output from comparator 50a to generate an FB_PWM signal, the duty ratio changes from 0.9 to 0.1 immediately after switching. On the other hand, as explained above, since an FF_PWM signal is fed to the primary circuit so that virtual Vin becomes 2.7 V, according to said formula (2), output potential Vout becomes
                                                                        V                out                            =                              VirtualVin                /                FBduty                                                                                        =                              2.7                ⁢                                                                  ⁢                                  V                  /                  0.1                                                                                                        =                              27                ⁢                                                                  ⁢                V                                                                        (        4        )            and output potential Vout overshoots.
The overshoot of said output potential Vout is cancelled when capacitor C1 is sufficiently discharged and potential V40 of the output terminal of transconductance amplifier 40 reaches a stable level of 0.91 V (corresponding to an FBduty of 0.9 in the step-up control mode), yet a ripple voltage is observed during this period.
That is, the duty ratio of the FB_PWM signal is set so that it is always 0.9. However, in practice, in the transient region immediately after switching of the control mode, a state with a duty ratio of 0.1 takes place, and a ripple voltage is observed during this period.
As explained above, for a switching power supply device in the prior art having a transconductance amplifier, at the time of switching from the step-down control mode to the step-up control mode, because a capacitor with a relatively large capacitance for phase compensation is connected to the output terminal of the transconductance amplifier, due to the influence of said capacitor, the potential of the output terminal of the amplifier cannot immediately follow the desired value. As a result, a ripple voltage takes place in the output. This is undesired.
The objective of the present invention is to solve the aforementioned problems of the prior art by providing a switching power supply device that has a reduced ripple voltage at the output when switching is performed between the step-up control mode and step-down control mode.